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Speed trap digital read-outs
#6

   

Here is the back-plane PCB design.

The first module in the sequence will have optically isolated inputs for serial data, clock and latch. The module will be powered by a 12V PSU snd includes a 5V regulator for the logic ICs. Again this is only present for the first module in the sequence.

All modules will have the TPIC5D596 shift register and the LED biasing resistors.

That’s the design completed - next the PCB manufacture, component assembly and system test :)

c
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Messages In This Thread
Speed trap digital read-outs - by Dr_C - 25th-Oct-24, 10:13 PM
RE: Speed trap digital read-outs - by Dr_C - 26th-Oct-24, 09:47 PM
RE: Speed trap digital read-outs - by Dr_C - 9th-Nov-24, 03:00 PM
RE: Speed trap digital read-outs - by Dr_C - 9th-Nov-24, 03:02 PM
RE: Speed trap digital read-outs - by dvd3500 - 10th-Nov-24, 06:09 PM
RE: Speed trap digital read-outs - by Dr_C - 10th-Nov-24, 07:13 PM
RE: Speed trap digital read-outs - by Dr_C - 12th-Nov-24, 12:58 PM
RE: Speed trap digital read-outs - by Dr_C - 23rd-Nov-24, 01:43 PM
RE: Speed trap digital read-outs - by Dr_C - 25th-Nov-24, 08:51 PM
RE: Speed trap digital read-outs - by Dr_C - 30th-Nov-24, 07:22 PM
RE: Speed trap digital read-outs - by Dr_C - 9th-Dec-24, 07:58 PM
RE: Speed trap digital read-outs - by Dr_C - 6th-Jan-25, 12:13 PM
RE: Speed trap digital read-outs - by Dr_C - 6th-Jan-25, 03:18 PM
RE: Speed trap digital read-outs - by Dr_C - 23rd-Jan-25, 02:12 PM

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