26th-Oct-24, 09:47 PM
For anyone interested in the technical details of this project, the plan is as follows:
1/ An ATtiny3226 will act as the core processor reading ID sensor pairs on each of the two lanes.
2/ The ID sensors will give arrival times as well as ID detection. From the timing information, and knowing the sensor spacing, the vehicle speed is calculated.
3/ The ATtiny will then communicate with the dispay modules (in this case 4inch vertical height) using a three signal serial bus. The dispays will be driven by 74HC596 serial-to-parallel shift registers.
All the hardware and firmware for each of the system components have been designed and tested. All that remains is the design of the pcb back-plane for the display modules and this has been tested, already, using smaller displays - yes, 0.2 inch ;)
Hopefully this project shouldn’t take too long to complete.
c
1/ An ATtiny3226 will act as the core processor reading ID sensor pairs on each of the two lanes.
2/ The ID sensors will give arrival times as well as ID detection. From the timing information, and knowing the sensor spacing, the vehicle speed is calculated.
3/ The ATtiny will then communicate with the dispay modules (in this case 4inch vertical height) using a three signal serial bus. The dispays will be driven by 74HC596 serial-to-parallel shift registers.
All the hardware and firmware for each of the system components have been designed and tested. All that remains is the design of the pcb back-plane for the display modules and this has been tested, already, using smaller displays - yes, 0.2 inch ;)
Hopefully this project shouldn’t take too long to complete.
c
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